Speaker: Jie Tang, Post-doctoral researcher, University of California Riverside
Time: 8:30- 9:30 am, Dec.23, 2014
Venue: Room 202, Second Floor, Office Building, Software Campus
Abstract：In order to build the high performance as well as energy efficient memory management, we have figured out the solutions targeting for both native and managed memory system. In the native side, we proposed the energy efficient hardware prefetching. Data prefetching has been a successful technique in high-performance computing platforms. However, the conventional wisdom is that they significantly increase energy consumption, and thus not suitable for resource limited embedded mobile systems. Contrary to the conventional wisdom, our findings demonstrate that as technology advances from 90nm to 32nm, prefetching can be energy-efficient while improving performance. Furthermore, we have developed a simple but effective analytical model to help system designers to identify the conditions for energy efficiency.
For the managed environment, we have studied how the memory management of Java Virtual Machine (JVM) can be improved by hardware acceleration and virtual space based parallelism. As a starting point, we design, implement, and evaluate specialized hardware instructions to accelerate Garbage Collection (GC) operations in JVM. We performed a profiling study on various GC algorithms to identify the GC performance hotspots. By moving these hotspot functions into hardware, we achieved an order of magnitude speedup and significant improvement on energy efficiency. As a second step, we designed Packer, a Parallel Garbage Collection Based on Virtual Spaces. Instead of physically dividing the heap into multiple spaces, Packer manages multiple virtual spaces in one physical space. With multiple virtual spaces, Packer offers efficient memory management. With one physical space, Packer avoids the problem of an inefficient space utilization. To reduce the garbage collection pause time, we also propose a novel parallelization method that is applicable to multiple virtual spaces. Specifically, we reduce the compacting GC parallelization problem into a discreted acyclic graph (DAG) traversal parallelization problem, and apply it to both normal and large object compaction.
Bio: Dr. Jie Tang is currently a post-doctoral researcher at the University of California Riverside. She received her B.E. From University of Defense Technology in 2006, and Ph.D. degree from the Beijing Institute of Technology in 2012, both in Computer Science. During her PhD study, from 2009 to 2011, she was a visiting researcher at the Embedded Systems Center at University of California, Irvine, USA, and was awarded the 2011 “Doctor Candidate Academic New Artist” by China Education of Ministry. Before joining UC Riverside, She was a research scientist at Intel China Runtime Technology Lab for one and half year. She is mainly doing research on Computer Architecture, Run-time System and Embedded system. She has published over 20 peer-reviewed publications and 9 of them have been indexed by SCI. She also has already established the cooperation with several Universities and Industry Research Centers home and abroad, including 微软 Research, Baidu Research and Inria in France. Meanwhile, she has been invited to serve on the Technical Program Committee of 5 conferences/workshop in her field and been invited to perform reviews for more than 40 leading journals and conferences internationally.